1. Field of the Invention
The present invention relates to an active matrix circuit, a method of driving an active matrix circuit, and a surface pressure distribution detecting apparatus.
2. Description of the Related Art
An active matrix circuit basically includes selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices. The active matrix circuit having above structure may be used, for example, in a liquid crystal display, a surface pressure distribution detecting apparatus, etc. When the active matrix circuit is used in a display device such as a liquid crystal display, the horizontal scanning circuit outputs an image signal to pixel electrodes connected to corresponding active devices. When the active matrix circuit is used in a surface pressure distribution detecting apparatus such as a fingerprint detector, the horizontal scanning circuit inputs a pressure signal applied to electrodes connected to corresponding active devices.
The horizontal scanning circuit described above includes a transfer circuit including a shift register which transfers a horizontal start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a horizontal clock signal thereby outputting control pulses. The vertical scanning circuit includes a vertical transfer circuit which transfers, in response to a vertical clock signal, a vertical start pulse from a first stage to a final stage in a stage-by-stage fashion. Conventionally, the start pulses and the clock signals are supplied to the transfer circuits from an external timing generator. However, use of an external timing generator results in complexity of the overall structure of a system using an active matrix circuit. Furthermore, the horizontal or vertical scanning circuit according to the conventional technique includes a voltage multiplying circuit for internally stepping up a low-voltage start pulse or clock pulse input from the outside and supplying resultant high-voltage pulses to the transfer circuit. However, in this voltage multiplying circuit, the clock signals supplied to the respective stages of the transfer circuit are stepped up using a single level shifter, and thus a very large load is imposed upon the level shifter. As a result, a large signal delay occurs and large power is consumed.
The above-described problems in the conventional technique can be solved according to aspects of the present invention as described below. According to a first aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the active matrix circuit being characterized in that: the vertical scanning circuit includes a transfer circuit for transferring an input start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a clock signal thereby generating a selection pulse, and also includes a start pulse generating circuit which internally generates a start pulse by processing a selection pulse output from the final stage of the transfer circuit and applies the resultant start pulse to the first stage of the transfer circuit.
According to a second aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the active matrix circuit being characterized in that: the horizontal scanning circuit includes a horizontal transfer circuit for transferring a horizontal start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a horizontal clock signal thereby outputting a control pulse; and the vertical scanning circuit includes a vertical transfer circuit for transferring a vertical start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a vertical clock signal and also includes a vertical clock signal generator which generates a vertical clock signal by processing a control pulse output from the final stage of the horizontal transfer circuit and supplies the resultant vertical clock signal to the vertical transfer circuit.
According to a third aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the active matrix circuit being characterized in that: the horizontal scanning circuit includes a transfer circuit for transferring an input start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a clock signal thereby generating a control pulse, and also includes a start pulse generating circuit which internally generates a start pulse by processing a control pulse output from the final stage of the transfer circuit and applies the resultant start pulse to the first stage of the transfer circuit.
According to a fourth aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the active matrix circuit being characterized in that: the horizontal scanning circuit includes a horizontal transfer circuit for transferring a horizontal start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a horizontal clock signal thereby outputting a control pulse; the vertical scanning circuit includes a vertical transfer circuit for transferring a vertical start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a vertical clock signal; and the active matrix circuit further comprises a reset circuit for, in response to a reset pulse supplied from the outside, forcedly resetting the horizontal transfer circuit and the vertical transfer circuit into their initial states.
According to a fifth aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the horizontal scanning circuit including a first horizontal transfer circuit for transferring a first start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a first clock signal thereby outputting a control pulse, the vertical scanning circuit including a second horizontal transfer circuit for transferring a second start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a second clock signal, the active matrix circuit being characterized in that: the active matrix circuit further comprises a voltage multiplying circuit for stepping up a low-voltage clock signal input from the outside and supplying a resultant high-voltage clock signal to respective stages of the transfer circuits, the voltage multiplying circuit including a plurality of level shifters for individually stepping up clock signals for the respective stages of the transfer circuit. Preferably, each level shifter performs a stepping-up operation in synchronization with the transferring operation of a corresponding stage of the transfer circuits. The on-off transition of the voltage multiplying operation of each level shifter is directly controlled by a pulse output from a corresponding stage of the transfer circuits.
According to a sixth aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the horizontal scanning circuit including a first horizontal transfer circuit for transferring a first start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a first clock signal thereby outputting a control pulse, the vertical scanning circuit including a second horizontal transfer circuit for transferring a second start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a second clock signal, the active matrix circuit being characterized in that: the active matrix circuit further comprises a voltage multiplying circuit for stepping up a low-voltage clock signal input from the outside and supplying a resultant high-voltage clock signal to respective stages of the transfer circuits, and the voltage multiplying circuit includes level shifters for individually stepping up a clock signal for respective sets of two or more stages of the transfer circuits. Preferably, each level shifter performs a stepping-up operation in synchronization with the transferring operation of a corresponding set of two or more stages of the transfer circuits.
According to a seventh aspect of the present invention, there is provided an active matrix circuit comprising selection lines extending along rows, signal lines extending along columns, active devices disposed at respective locations where the selection lines and the signal lines cross each other, a vertical scanning circuit for outputting selection pulses to sequentially scan the selection lines thereby selecting active devices, and a horizontal scanning circuit for outputting control pulses to open or close the respective signal lines thereby inputting or outputting a signal to selected active devices, the horizontal scanning circuit including a transfer circuit for transferring a start pulse from a first stage to a final stage in a stage-by-stage fashion in response to a clock signal thereby outputting a control pulse, the active matrix circuit being characterized in that: the active matrix circuit further comprises a voltage multiplying circuit for stepping up a low-voltage clock signal input from the outside and supplying a resultant high-voltage clock signal to respective stages of the transfer circuit, the voltage multiplying circuit includes a plurality of level shifters for separately stepping up clock signals for the respective stages of the transfer circuit, each stage of the transfer circuit performs a transferring operation in response to a clock signal supplied from a corresponding level shifter thereby outputting a control pulse, and the active matrix circuit further comprises a switch for sampling the clock signal in response to the control pulse and controlling the on/off operation associated with the respective signal lines.
In the active matrix circuit according to the first aspect of the present invention, after the transfer operation is started, the vertical start pulse is internally generated so that the transfer operation can be performed starting from the first-stage vertical line (first row). The next start pulse is generated by processing a selection pulse output from the final stage of the vertical transfer circuit and the generated start pulse is supplied to the first stage of the vertical transfer circuit. The operation performed via such a loop in the circuit minimizes the necessity of external inputs and allows a reduction in power consumption of the circuit. In the active matrix circuit according to the second aspect of the present invention, the first-stage vertical line is operated in response to starting of the transfer operation. Thereafter, in the operation of the second and following stages, the vertical clock signal is internally generated by processing the control pulse output from the horizontal transfer circuit so that the start pulse is transferred from one stage to the next stage in response to the internally generated vertical clock signal. Because the vertical clock signal is internally generated, the necessity of the external inputs is reduced and a reduction in the power consumption of the circuit is achieved. In the active matrix circuit according to the third aspect of the present invention, after the operation is started in response to a horizontal pulse applied to the horizontal transfer circuit, following horizontal clock signals are internally generated one by one thereby maintaining the transfer operation. Because the transfer operation is performed via the looped path in the circuit, the necessity of the external inputs is reduced and a reduction in the power consumption of the circuit is achieved. In the active matrix circuit according to the fourth aspect of the present invention, the voltages in the transfer circuits are reset by a reset pulse input from the outside. This makes it possible to forcedly initialize the transfer state at any desired point of time. That is, resetting the voltages in the transfer circuit into initial values regardless of the current values allows a data transfer operation to be started at any desired point of time. This allows a reduction in the data processing time. In the active matrix circuit according to the fifth aspect of the present invention, the voltage multiplying circuit steps up the low-voltage clock signal input from the outside and supplies a resultant high-voltage clock signal to the respective stages of the shift register of the transfer circuit, wherein the voltage multiplying circuit includes level shifters provided for the respective stages of the transfer circuit so that each level shifter individually steps up a clock signal for a corresponding stage. Because each level shifter performs the stepping-up operation only when a corresponding stage of the transfer circuit performs the transfer operation, a reduction in the power consumption is achieved. This configuration, in which one level shifter is provided for one stage of a shift register of a transfer circuit, is useful in particular when it is applied to a first stage or a final stage. In the active matrix circuit according to the sixth aspect of the present invention, the voltage multiplying circuit includes level shifters for individually stepping up a clock signal for respective sets of two or more stages of the transfer circuits. This technique allows a reduction in the number of level shifters compared with a case in which one level shifter is provided for each stage of the shift register of the transfer circuit, and thus the voltage multiplying circuit can be realized in a simpler fashion. This technique is useful in particular when it is applied to middle stages of the transfer circuit. In the active matrix circuit according to the seventh aspect of the present invention, the voltage multiplying circuit includes a plurality of level shifters for individually stepping up clock signals for the respective stages of the horizontal transfer circuit, and each stage of the horizontal transfer circuit performs a transferring operation in response to a clock signal supplied from a corresponding level shifter thereby outputting a control pulse. Furthermore, in this seventh aspect of the present invention, the active matrix circuit further comprises a switch for sampling the clock signal in response to the control pulse and controlling the on/off operation associated with the respective signal lines. The stepped-up clock signal is directly used to open and close the switch, and thus a reduction in the total signal propagation delay in the circuit can be achieved.